a) Field of the Invention
The present invention relates to a bonding pad structure of a semiconductor device such as an LSI, and more particularly to a bonding pad structure having n (n is an integer of 3 or larger) pad layers and (n-1) interlayer insulating films.
b) Description of the Related Art
A most common bonding pad structure has large bonding pads formed on the highest-level insulating film among a plurality of insulating films. With such a bonding pad lamination structure, if a lamination film including a coated insulating film such as organic or inorganic SOG (spin on glass) is used as the insulating film or films under the pad layer, peel-off or cracks of the coated insulating film may occur because of heat and pressure during the bonding, thereby lowering the reliability.
In order to solve this problem, semiconductor devices having a bonding pad area such as shown in FIGS. 8 to 11 are known (refer to JP-A-9-219451).
In the semiconductor device shown in FIG. 8, a first-level (first-layer) insulating film 2 is formed on the surface of a semiconductor substrate 1. On this first-level insulating film 2, a plurality of first-level wiring layers 3a and a plurality of first-level pad layers 3b are formed. The wiring layer 3a is formed in an inner wiring area A including an integrated circuit formed on the semiconductor substrate 1. The pad layer 3b is formed in a bonding pad area B disposed around the inner wiring area A.
On the first-level insulating film 2, a first-level interlayer insulating film 4 is formed covering the plurality of wiring layers 3a and pad layers 3b. The upper surface of the first-level interlayer insulating film 4 is planarized by chemical mechanical polishing (CMP). A contact hole 4A and a plurality of contact holes 4B are formed through the first-level interlayer insulating film 4 by photolithography and dry etching in the areas corresponding to the wiring layer 3a and pad layer 3b. First-level contact plugs 5a and 5b are filled in the contact holes 4A and 4B. These contact plugs 5a and 5b are formed by forming a conductive layer of tungsten (W) or the like on the insulating film 4 and in the contact holes 4A and 4B, and thereafter etching back the conductive layer until the upper surface of the insulating film 4 is exposed.
On the first-level interlayer insulating film 4, a second-level wiring layer 6a and a second-level pad layer 6b are formed. The wiring layer 6a is connected via the contact plug 5a to the wiring layer 3a, and the pad layer 6b is connected via a plurality of contact plugs 5b to the pad layer 3b.
On the first-level interlayer insulating film 4, a second-level interlayer insulating film 7 is formed covering the second-level wiring layer 6a and second-level pad layer 6b. The upper surface of the second-level interlayer insulating film 7 is planarized by CMP. A contact hole 7A and a plurality of contact holes 7B are formed through the second-level interlayer insulating film 7 by photolithography and dry etching in the areas corresponding to the second-level wiring layer 6a and second-level pad layer 6b. Second-level contact plugs 8a and 8b are filled in the contact holes 7A and 7B. These contact plugs 8a and 8b are formed by a process similar to that of forming the first-level contact plugs 5a and 5b described above.
On the second-level interlayer insulating film 7, a third-level wiring layer 9a and a third-level pad layer 9b are formed. The third-level wiring layer 9a is connected via the second-level contact plug 8a to the second-level wiring layer 6a, and the third-level pad layer 9b is connected via a plurality of second-level contact plugs 8b to the second-level pad layer 6b.
In the semiconductor device shown in FIG. 9, the wring structure in the inner wiring area A is similar to that in the inner wiring area A shown in FIG. 8. In FIG. 9, like elements to those shown in FIG. 8 are represented by using identical reference symbols, and the description thereof is omitted.
In the bonding pad area B shown in FIG. 9, the insulating film 4 is formed on the insulating film 2, and the insulating film 7 is formed on the insulating film 4. On the insulating film 7, a pad layer 9b is formed by using the same process as that of forming the wiring layer 9a.
In the semiconductor device shown in FIG. 10, the wring structure in the inner wiring area A is similar to that in the inner wiring area A shown in FIG. 8. In FIG. 10, like elements to those shown in FIG. 8 are represented by using identical reference symbols, and the description thereof is omitted.
In the bonding pad area B shown in FIG. 10, the insulating film 4 is formed on the insulating film 2, and on the insulating film 4 the pad layer 6b is formed by using the same process as that of forming the wiring layer 6a.
On the insulating film 4, the insulating film 7 is formed covering the wiring layer 6a and pad layer 6b. The upper surface of the insulating film 7 is planarized by CMP. Contact holes 7A and 7B are formed through the insulating film 7 by photolithography and dry etching in the areas corresponding to the wiring layer 6a and layer 6b. The contact hole 7S is made larger in size than the contact hole 7A for the later process of bonding a bonding wire.
After a conductive layer of W or the like is formed on the insulating film 7 and in the contact holes 7A and 7S, the conductive layer is etched back until the upper surface of the insulating film is exposed. A contact plug 8a made of conductive material such as W is therefore formed in the contact hole 7A. At this time, although a thin conductive layer (not shown) is left on the side wall of the contact hole 7S, most of the conductive layer are etched and removed during the etch-back process so that the upper surface of the pad layer 6b is exposed in the contact hole 7S.
A wiring layer is deposited on the insulating film 7, covering the contact plug 8a and the contact hole 7S, and patterned to form a wiring layer 9a and a pad layer 9b. The pad layer 9b directly contacts the pad layer 6b in the contact hole 7S.
In the semiconductor device shown in FIG. 11, on the insulating film 2 covering the surface of the substrate 1, the first-level wiring layer 3a and the first-level pad layer 3b are formed by the method similar to that described with reference to FIG. 8. On the insulating film 2, the insulating film 4 is formed covering the wiring layer 3a and pad layer 3b. The upper surface of the insulating film 4 is planarized by CMP.
Similar to the contact holes 7A and 7S described with reference to FIG. 10, a small size contact hole 4A and a large size contact hole 4S are formed through the insulating film 4 in the areas corresponding to the wiring layer 3a and pad layer 3b. Similar to the contact plug 8a described with reference to FIG. 10, a contact plug 5a made of conductive material such as W is formed in the contact hole 4A. Similar to the wiring layer 9a and pad layer 9b described with reference to FIG. 10, a second-level wiring layer 6a and a second-level pad layer 6b are formed on the insulating film 4. The wiring layer 6a is connected via the contact plug 5a to the wiring layer 3a, and the pad layer 6b is directly connected to the pad layer 3b in the contact hole 4S.
On the insulating film 4, an insulating film 7 is formed covering the wiring layer 6a and pad layer 6b. The upper surface of the insulating film 7 is planarized by CMP. A small size contact hole 7A corresponding to the wiring layer 6a and a large size contact hole 7S corresponding to the pad layer 6b are formed through the insulating layer 7 by photolithography and dry etching.
In the semiconductor device shown in FIG. 11, a depth a of the contact hole 7A is smaller than a depth b of the contact hole 7S. During the selective dry etching of forming the contact holes 7A and 7S, it is necessary to over-etch the contact hole 7A to the depth b after the depth a of the contact hole 7S is obtained. Therefore, the size of the contact hole 7A becomes larger than the design value.
In the semiconductor device shown in FIG. 8, the first-level contact holes 4A and 4B have substantially the same depth, and the second-level contact holes 7A and 7B also have substantially the same depth. In the semiconductor device shown in FIG. 9, no contact hole is formed in the bonding pad area. In the semiconductor device shown in FIG. 10, the contact holes 7A and 7S have substantially the same depth.
In the bonding pad structure shown in FIG. 8, a single bonding pad layer 9b is bonded with a bonding wire. It is therefore not easy to have a sufficient bonding pad strength. For example, if an Au wire is bonded to the pad layer 9b made of Al alloy, a lowered shearing stress is sometimes found by a shear test after the pad layer is exposed to a high temperature. The reason for this may be ascribed to a thin pad layer 9b and an insufficient supply of Al to the bonded portion (the details of which are to be referred to JP-A-7-335690).
In the bonding pad structures shown in FIGS. 9 and 10, if a lamination film including a coated insulating film such as organic or inorganic SOG (spin on glass) is used as the insulating films 4 and 7 or the insulating film 4 under the pad layer 9b, peel-off or cracks of the coated insulating film may occur because of heat and pressure during the bonding, thereby lowering the reliability.